ATRIA LOGIC, INC.

OVERVIEW

The AL-H264D-REFD reference design is System-on-Chip (SoC) implementation of H.264/AVC Baseline Profile
Decoder with an ARM Cortex-M1 or an Altera NIOS embedded processor along with peripheral logic. This
reference design is implemented on Altera Cyclone-III FPGA development board.

Atria Logic offers complete set of IP cores to fasten development of H.264 Video Decoder System on ASIC or
FPGA.

H.264 video processing is fairly complex and computationally intensive. Besides the memory bandwidth needs,
the video processing requires constant inflow of bitstream data and outflow of decoded data either to be stored or
displayed. This reference design is build using various IP’s that would accommodate a video decoding demo. In
this particular reference design apart from the H.264/AVC Baseline Profile Decoder the design has a multi-port
DDR controller, an Ethernet MAC for input bitstream, Flash controller to access alternate bitstream from onboard
flash, an ARM processor for control of all the IP and a LCD display controller to output the decoded pixels. Other
than the ARM processor all the other IP is designed by Atria Logic (please refer to the product documentation for
all the IP mentioned here and various other IP developed by Atria Logic at www.atrialogic.com).

Designed for easy reuse in ASIC and FPGA implementations, the design is strictly synchronous with
positive-edge clocking. The implementation is completely programmable SoC solution. It is operable both in
micro-code free hardwire mode or in SW assist mode in ARM/NIOS embedded processor system.