ATRIA LOGIC, INC. Silicon On Chip IP

The AL_DDR12_CTRL Memory Controller Core implements an efficient and pipelined interface to
DDR-I and DDR-II SDRAM devices targeted for System-on-Chip (SoC) and FPGA platforms. The
memory controller core is fully configurable to accommodate all the features in the JEDEC
specification. The design has set of programmable registers to define the functionality of the
memory controller and to configure the DRAM. On power-up the controller performs initialization of
the DRAM based on the programmed paramerters in the registers. On completion of the
initialization sequence, the DRAM will be ready to process READ/WRITE requests from the user.

The AL-USB2D-CTRL fully synthesizable core implements a complete high/full-speed
(480/12Mps) peripheral controller that interfaces to a UTMI USB port transceiver on one side and
to a system’s microprocessor on the other. It is user-configurable for up to 15 IN and OUT
endpoints, and includes power management and remote wake-up functions.