ATRIA LOGIC, INC. H.264 Decoder

OVERVIEW

The AL-H264D-CTRL core is a feature rich RTL implementation of H.264/AVC Baseline Profile Decoder algorithm
for high quality multimedia services on limited bandwidth network. The core processes video bitstream from
external memory such as SRAM or DDR1/2 and writes decoded frames back to external memory. It supports
video resolutions from SQCIF to HD.

Designed for easy reuse in ASIC and FPGA implementations, the design is strictly synchronous with
positive-edge clocking. The implementation is completely programmable SoC solution. It is operable both in
micro-code free hardwire mode or in SW assist mode in ARM embedded processor system.

The core decodes CIF @ 30fps with a single 12 MHz clock source. The design is a multi clock domain design
with clock gating enabled to switch off and on certain modules and conserve power. The core is also designed for
very low latency processing yet optimal gate count.