Memory Controller IP

QDR IV XP PHY + MEMORY CONTROLLER IP

High speed QDR IV Extreme Performance (XP) PHY and memory controller with 800MHz memory interface and 200MHz user interface, for next generation high-performance memories.

HYBRID MEMORY CUBE VERIFICATION IP

Reusable, user-friendly, configurable verification component IP in SystemVerilog at the IP or system level, for FPGA and SoC implementations. 

DDR-I/II/III CONTROLLER IP CORE

Fully configurable to JEDEC specifications, with efficient and pipelined interface to DDR-I and DDR-II SDRAM devices for FPGA and SoC implementations.

  • Products

    • Multimedia

  • H.264 UHD Hi422 Intra Video Decoder
  • H.264 UHD Hi422 Intra Video Encoder
  • H.264 Low Power & Low Latency HW Video Decoder
  • Low Power ARM AV Player
  • H.264 Streaming Video Decoder Reference Design
  • H.264 Software Video Encoder
  • MPEG-2 Software Video Encoder

    • Memory Controller

  • QDRIV XP PHY + Memory Controller IP
  • Hybrid Memory Cube (HMC) VIP
  • DDR-I/II/III Controller IP

    • Standard Bus Architecture

  • PCIe Gen1/2 PHY IP
  • NVMe Validation Test Suite
  • USB 2.0 Controller IP
  • 10/100/1000Mbps Ethernet MAC IP
  • I2C Master/Slave Controller IP

    • Heterogenous Processing

  • OpenCL, OpenCV Framework
  • Dewarping of Fisheye images
  • Services
  • Hardware Services
  • Software Services