Overview

DDRI/II/III Memory Controller Core implements an efficient and pipelined interface to DDR-I, DDRII and DDR-III SDRAM devices targeted for System-on-Chip (SoC) and FPGA platforms. The memory controller core is fully configurable to accommodate all the features in the JEDEC specification. The design has set of programmable registers to define the functionality of the memory controller and to configure the DRAM. On power-up the controller performs initialization of the DRAM based on the programmed paramerters in the registers. On completion of the initialization sequence, the DRAM will be ready to process READ/WRITE requests from the user. In case of multiple port access, an efficient Arbiter is used with programmable management scheme to have a fair arbitration. The controller also provides logic to support low-power applications by implementing SELF REFRESH and POWER-DOWN modes.

The controller core has the following modules:

• Control and Timing Engine
• DRAM Initialization Engine
• Command Generation Engine
• Address Generation and Bank Management
• Refresh Generation Engine
• Multiport Weighted Round-robin Arbiter
• Write Path and Read Capture Logic
• Calibration Logic
• PHY Logic for DDR I/O

The AL_DDR12_CTRL Core is designed for performance with low latencies and maximum bandwidth allocation for up to 16 requestors. The AL_DDR12_CTRL Core is highly configurable allowing the user with several options such as: DRAM width, DRAM instance count, DRAM speed grade, DRAM CAS latencies, number of user ports for DRAM access. The Controller Core flexible user interfaces such as: Command/Data FIFO or AMBA-AHB or Altera Avalon Slave interfaces for easy SoC integration.

Block Diagram